In gate-array-based ASIC, transistors are predefined on the silicon wafer . The Base cell is the smallest element that is replicated. The base array consists of predefined pattern of transistors. They are also known as Masked Gate Array (MGA). In this type only layers which define the interconnect between transistors are defined by the designer using custom masks. Designer chooses from a gate-array library predesigned and precharacterized logic cells (often called macros).
Since only metal interconnections are unique for MGA, we can use prefabricated wafers (with completed transistor layers) (Smith, 1997: 11). Channeled gate array There is space between the rows of transistors for wiring. Here only the interconnect is customized and uses predefined spaces between rows (Smith, 1997: 12). (Smith, 1997) Channelless gate array They are also known as sea-of-gates or SOG arrays. Here, there are no predefined areas set aside for routing between cells.
The contact layer that defines the connections between metal1 and transistors is customized. When transistor area is used for routing, there should not be any contacts to the device underneath (Smith, 1997: 12). (Smith, 1997) Structured gate array or embedded gate array It combines the features of CBIC and MGA. Since MGA has only fixed gate-array base cell, it is difficult to implement memory blocks. Here, some IC area is set aside and dedicated to a specific function like memory (Smith, 1997: 13).